NOC DV Sr Engineer

Overview

Verify next-generation infrastructure IPs, including DDRSS and memory controllers, for system-on-chip products used in smartphones, tablets and other product categories. Plan and implement IP, cluster and formal verification flows and coordinate with Design and SoC teams throughout the IP development cycle.

What you'll do

• Own the design verification testbench and associated collaterals, including checkers, trackers, scoreboards, assertions and functional coverage.
• Develop test plans and test cases to cover the design feature set.
• Follow up with stakeholders on code coverage and functional coverage closure at different testbench levels.
• Work with System Architects, Design and emulation teams on failure debugging and code/functional coverage closure.
• Debug regression signatures and identify bug fixes.
• Own quality sign-off and required documentation.
• Develop and deploy validation scripts and tools using Certitude, VC Formal and VPlan.
• Debug and root-cause post-silicon issues with Design, Software and test teams.
• Work with the SoC-level performance modeling team on latency and bandwidth analysis.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or a related field and 2+ years of Hardware Engineering or related work experience, or Master's degree in those fields and 1+ year of Hardware Engineering or related work experience, or a PhD in those fields.
• Bachelor's or Master's degree in Electronics & Communication or Micro Electronics.
• 3+ Years of Experience in IP verification or related.
• Strong debugging, analytical and problem-solving skills.
• Expertise in UVM-based verification.
• Knowledge of ARM bus protocols, virtual memory concepts and SoC system architecture.
• Experience developing monitors, scoreboards and sequencers using scripts, SystemVerilog, UVM and methodologies to increase the rate at which bugs are found and resolved.
• Communication and collaboration skills to work with a large worldwide design organization.
• Experience with UVM and ARM bus protocols.

Nice to have

• Experience in designs optimized for low power, including dynamic clock gating and logic/memory power collapse.
• Experience verifying designs meeting Automotive Safety Integrity Levels (ASIL).
• Proficiency in scripting languages, Python or Perl, for automation initiatives.
• Experience with C, C++ or SystemC for performance models.
• Post-silicon bring-up and hardware-software debugging experience.
• Knowledge and exposure to silicon debug toolchains.

Details

• Location: Bangalore, India.