Mixed- Signal Systems and Verification Engineer

Overview

Develop and verify analog behavioral models and mixed-signal systems for analog/RF blocks using SystemVerilog and related AMS technologies.

What you'll do

• Develop simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog.
• Verify behavioral models against analog schematics.
• Integrate behavioral models with RTL.
• Verify analog functionality against design specifications.
• Code test benches, test scenarios, and assertions.
• Document modeling and verification results for formal review.

What you'll need

• Experience developing and verifying real-numbered behavioral models in SystemVerilog.
• Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS.
• Basic understanding of AMS blocks including filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, and mixers.
• Experience with low-power architecture.
• Experience with Cadence Virtuoso Schematic Composer and ADE.
• Experience with analog assertion-based verification.
• Experience writing scripts in Perl or Python.

Nice to have

• Experience in testbench development.
• Experience with FPGA prototyping.
• DSP experience.

Details

• New graduates are strongly encouraged to apply.
• Location: Bangalore.