Senior Engineer (Level 1)- Verification

Overview

The Senior Engineer (Level 1)- Verification role focuses on SOC, IP, and block-level functional verification using SystemVerilog and UVM.

What you'll do

• Develop test plans, testbench components, verification environments, interface agents, and scoreboards in UVM.
• Execute SOC/IP verification projects.
• Debug RTL and testbench issues and test failures.
• Close coverage and bug reports as part of verification closure.
• Develop and maintain scripts.
• Understand customer dynamic environment changes and adopt runtime changes in schedule and design.

What you'll need

• 4 to 8 years of experience in SOC/IP/block-level functional verification using SystemVerilog/UVM.
• Strong knowledge of UVM, advanced UVM, and SystemVerilog.
• Experience developing test plans, testbench components, verification environments, interface agents, and scoreboards in UVM.
• Experience executing at least 1 to 2 SOC/IP verification projects.
• Knowledge of at least one industry-standard protocol such as Ethernet, PCIe, MIPI, USB, AMBA, or similar.
• Skills to debug RTL and testbench issues and test failures.
• Experience with verification closure by closing coverage and bug reports.
• Knowledge of script development and maintenance.

Details

• Location: Bangalore, India.
• Employment type: Full time.
• Job category: Engineering Services.