Senior Engineer II - Verification

Overview

Senior PCIe Verification Engineer to build and run verification environments for next-generation Data Center Storage products, including enterprise-class PCIe Gen5/6/7 memory controllers and other PCIe/CXL-based SoC products.

What you'll do

• Define verification plans and build testbenches using UVM/System Verilog for PCIe Gen5/6/7 IP.
• Interpret PCIe protocol specifications to develop and execute verification plans in simulation environments.
• Integrate and configure third-party PCIe Verification IPs (e.g., Synopsys, Cadence) for Gen5/6/7 verification.
• Develop test cases, checkers, and functional/code coverage models per the verification plan.
• Collaborate with firmware, emulation, and silicon validation teams; support pre-silicon and post-silicon bring-up/debug.

What you'll need

• Bachelor's/master's degree in Electronics/VLSI Engineering.
• 6+ years of RTL verification experience, including 2+ years specifically in PCIe protocol verification.
• Strong hands-on expertise in UVM/System Verilog-based testbench development.
• Domain expertise in PCIe Gen5/6/7 protocols, focusing on Transaction Layer verification.
• Expertise in verifying PCIe features, including compliance verification on PCIe/CXL EP/RC.
• Knowledge of AMBA AXI/AHB/APB protocols.
• Expertise in test plan creation, testbench architecture, and test scenario development, including functional coverage and code coverage management.
• Strong analytical and problem-solving skills, with a proven ability to work independently.
• Excellent written and verbal communication and documentation skills.

Details

• Location: Bangalore, India.
• Travel: 0% - 25%.