Senior Staff Engineer Verification

Overview

Senior Verification Engineer role focused on ASIC/SoC functional verification of DSP and arithmetic datapaths, with SystemVerilog/UVM environments and MATLAB/C reference model integration for RTL correlation.

What you'll do

• Develop and own SystemVerilog/UVM-based verification environments, including scoreboards, sequences, RAL, regressions, and coverage closure.
• Verify DSP and arithmetic datapath blocks such as filters, transforms, sensor-processing, and measurement-chain subsystems.
• Integrate C/MATLAB reference models using DPI and drive automated RTL-to-model correlation.
• Perform regression management, failure triage, root-cause analysis, and verification sign-off activities.
• Support silicon bring-up and collaborate with design teams to resolve functional issues.

What you'll need

• 7+ years of experience in ASIC/SoC functional verification.
• Strong expertise in SystemVerilog, UVM, Functional Coverage, Code Coverage, and RAL.
• Solid understanding of fixed-point arithmetic, including Q-formats, bit growth, rounding, truncation, saturation, and quantization effects.
• Hands-on experience with MATLAB/Simulink, Fixed-Point Designer, and model-based verification.
• Ability to analyze filter behavior, including impulse/step response, latency, saturation, and recovery.
• Experience with constrained-random verification, directed testing, and large-scale regression debugging.

Details

• Location: Bangalore BTP.