ASIC Verification Engineer

Overview

ASIC Verification Engineer responsible for planning and implementing functional verification for IP/Cluster/SOC designs used in Graphics Processors and Tegra SoCs.

What you'll do

• Own ASIC verification of IP/Cluster for complex RTL designs.
• Plan and implement regression plans for code and functional coverage closure.
• Perform pre-silicon validation using XPROP simulations and GLS.
• Augment verification with dynamic simulations and/or formal verification techniques.
• Ensure functional and code coverage against specifications.
• Partner with FPGA and S/W teams to ensure S/W is tested.
• Support post-silicon verification and debug.

What you'll need

• BS/MS or equivalent experience.
• 1+ years of design experience.
• Experience in ASIC verification of complex design units for at least one or two projects.
• Background with design and verification tools (VCS or equivalent; debug tools like Debussy, GDB).
• Exposure to SystemVerilog and UVM-based methodology for ASIC verification is highly desired.
• Scripting knowledge (Python/Perl/shell).
• Good interpersonal skills and ability to work as part of a team.

Nice to have

• Knowledge of memory controllers or prior verification experience involving memory access.
• Good debugging and problem-solving skills.

Details

• Hybrid work mode (#LI-Hybrid).