LPASS Design Verification Engineer

Overview

LPASS Design Verification Engineer for Qualcomm’s hardware audio subsystem. You will own verification for LPASS features using modern DV tools and testbench development.

What you'll do

• Own DV activities for one or more LPASS core features.
• Develop a robust, feature/DUT-specific testbench.
• Apply DV methodologies such as formal, simulation, and emulation.
• Continuously improve testbench quality and verification efficiency.
• Ensure bug-free silicon for tape out supporting user experience on Snapdragon devices.

What you'll need

• 1-2 years of VLSI industry experience.
• Strong debugging and analytical skills.
• Knowledge of HDLs such as Verilog and SystemVerilog.
• Ability to develop SV/UVM based testbenches.
• Skill in debugging RTL/TB issues using Verdi or similar tools.
• Proficiency in scripting with Perl and/or Python.

Details

• Location: Bangalore, India.