Lead STA Engineer

Overview

Lead static timing analysis for complex ASIC/SoC designs, drive timing closure and signoff, develop methodologies, and guide a small STA engineering team.

What you'll do

• Create, validate, and maintain SDC constraints at block and full-chip levels.
• Perform MCMM timing analysis across PVT variations.
• Debug setup, hold, transition, and path-based violations.
• Drive timing closure through timing ECO generation and evaluation.
• Collaborate with RTL, physical design, DFT, architecture, and front-end teams.
• Develop and support EDA implementation flows and script-based automation.
• Lead a small team of STA engineers and perform IP-level synthesis.

What you'll need

• 7+ years of hands-on STA experience for complex ASIC/SoC designs.
• Master's or bachelor's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• Experience developing multi-mode timing constraints and completing timing signoff for advanced technology nodes.
• Experience leading STA efforts through multiple successful tape-outs.
• Expertise with Synopsys PrimeTime or Cadence Tempus.
• Knowledge of digital design, clocking architectures, low-power techniques, and SDC.
• Proficiency in Perl, Python, or TCL scripting.

Details

• Location: Bangalore.