Senior Engineer II - Backend Implementation

Overview

Senior Backend Implementation Engineer for the Microchip AES Design team, performing STA for larger SoCs and supporting timing closure and low-power checks.

What you'll do

• Generate timing constraints (SDC) and support timing closure for multiple blocks and top level.
• Perform STA for full-chip and subsystem multi-million hierarchical complex designs.
• Develop constraints/SDC and run pre- and post-layout timing closure.
• Execute CLP and LEC at both full-chip and block levels.
• Optimize design performance using timing closure and power optimization approaches.
• Insert DFT logic for block and top level and analyze physical timing challenges for placement & CTS.

What you'll need

• 7+ years of STA experience in a fast-paced environment.
• B.E/B.Tech/M.Tech in Electronics.
• Experience with STA and timing closure, including static timing/crosstalk analysis.
• Must have understanding of DFT insertion.
• Skills with synthesis and STA tools including Genus, Fusion Compiler, Primetime, or Tempus.
• Strong programming knowledge in Perl, TCL, and/or Shell and Python scripting.
• Good understanding of Verilog.

Details

• Location: Bangalore, India.
• Travel time: 0% - 25%.