Senior STA Engineer

Overview

Senior STA Engineer responsible for static timing analysis, timing signoff, and timing closure for complex ASIC/SoC designs.

What you'll do

• Own STA and timing signoff activities from synthesis through physical design and tape-out.
• Run MCMM/MMMC timing analysis across functional and test modes.
• Analyze and debug timing violations including setup, hold, recovery, removal, min/max, and clock-related issues.
• Develop, review, and validate SDC constraints (clocks, generated clocks, I/O delays, false paths, multicycle paths, timing exceptions).
• Perform clock tree/timing analysis for skew, latency, uncertainty, jitter, and clock reconvergence.
• Drive timing closure with RTL, synthesis, physical design, and ECO teams and support timing ECOs.
• Build Tcl/Python automation for STA analysis and report generation.

What you'll need

• 4–8 years of experience (as stated in the posting).
• Expertise in static timing analysis and timing closure.
• Hands-on experience with Synopsys PrimeTime or Cadence Tempus (or equivalent STA tools).
• Strong knowledge of SDC constraints and timing exceptions.
• Expertise in ASIC/SoC design, synthesis, physical design, and signoff flows.
• Proficiency in Tcl scripting; Python/Perl scripting is an advantage.
• Understanding of OCV/AOCV/POCV, CPPR, SI/crosstalk, derating, and variation-aware timing.

Details

• Location: Ahmedabad, Gujarat, India.
• Employment type: Full-time.