Lead NSP STA/Timing Engineer

Overview

Lead NSP STA/Timing Engineer role focused on setting up and optimizing Static Timing Analysis (STA) flows, timing validation, and convergence across multi-mode, multi-voltage designs.

What you'll do

• Own STA setup, convergence, reviews, and signoff for multi-mode and multi-voltage domain designs.
• Perform timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice-to-STA correlation.
• Evaluate timing methodologies/tools across designs and technology nodes.
• Develop STA/PD tool automation scripts for methodology development.

What you'll need

• Have 7–14 years of experience in STA/Timing (preferred).
• Hold a B.Tech/M.Tech/MS in Electrical/Electronics/Microelectronics/VLSI.
• Have experience with design automation using TCL/Perl/Python.
• Be familiar with digital flow implementation from RTL to GDS using ICC and Innovus/PrimeTime/Tempus.
• Be familiar with process technology enablement including Hspice/FineSim and Monte Carlo.
• Have good technical writing and communication skills for cross-collaborative work.

Details

• Location: Bangalore, India.