NPU STA/Timing Engineer (Senior/Lead)

Overview

Senior/Lead NPU STA/Timing Engineer role focused on setting up STA flows, performing timing analysis, and driving convergence for multi-mode, multi-voltage designs.

What you'll do

• Set up STA flows, including convergence, reviews, and signoff for multi-mode, multi-voltage domain designs.
• Perform timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus.
• Run PrimeTime and/or Tempus for STA flow optimization and run Spice-to-STA correlation.
• Evaluate timing methodologies/tools across different designs and technology nodes.
• Develop automation scripts within STA/PD tools for methodology development.
• Work on timing convergence at chip level and hard-macro level.

What you'll need

• Have a Bachelor’s degree in a relevant field plus 3+ years of hardware engineering experience (or Master’s with 2+ years, or PhD with 1+ year).
• Have experience in design automation using TCL/Perl/Python.
• Be familiar with digital flow design from RTL to GDS using ICC and Innovus/Innovous (as written).
• Know process technology enablement including circuit simulations using Hspice/FineSim and Monte Carlo.
• Have good technical writing and communication skills for cross-collaborative environments.
• Have knowledge of timing constraints and handling latch transparency and path types (0-cycle, multi-cycle paths).

Details

• Location: Bangalore, India.