Senior PD Engineer: Synthesis & STA

Overview

Senior VLSI PD Engineer specializing in logic synthesis and STA, owning synthesis execution and signoff for key blocks and sub-chips. You’ll partner with RTL and expand into physical-design adjacent areas like PNR and timing convergence.

What you'll do

• Drive end-to-end logic synthesis for designated blocks and sub-chips and optimize area, power, and performance.
• Define, execute, and monitor sanity checks to achieve synthesis signoff quality.
• Collaborate with RTL teams to deliver clean, fully linted netlists before handoff.
• Analyze timing paths to control Levels of Logic (LOL) for high-frequency targets.
• Provide RTL guidance and structural/micro-architecture recommendations to improve netlist quality.
• Participate in physical-implementation adjacencies including PNR, STA, and full-chip timing convergence.

What you'll need

• 5 to 8 years’ experience in ASIC/SoC logic synthesis and static timing analysis.
• Hands-on logic synthesis tool experience, with a preference for Cadence Genus.
• STA signoff tool proficiency (Tempus, PrimeTime).
• Knowledge of STA, timing constraints (SDC), delay calculation, and MMMC analysis.
• Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.
• Ability to analyze datapath architectures and recommend RTL changes to reduce logic depth.
• Scripting/automation proficiency in Tcl, Python, or Perl.

Nice to have

• Prior exposure to PNR flows (e.g., Innovus, ICC2) and understanding of synthesis impact on congestion.
• Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).
• Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their synthesis/timing challenges.

Details

• Location: Bangalore, India with Hybrid / Remote indicated in the ATS.