Senior Manager - Design Engineering

Overview

Senior Manager in the CBU Product Development team providing technical leadership for communication semiconductor devices or subsystems. The role will help establish and scale CBU’s Silicon Design Center in India while defining the technical direction and engineering culture of the organization.

What you'll do

• Lead and develop a team of 20+ engineers.
• Manage resource allocation, performance reviews, and technical career growth.
• Drive end-to-end RTL design execution, from concept through architecture, coding, verification, synthesis, sign-off, and silicon bring-up support.
• Serve as a technical authority for digital design, ensuring high standards in quality, performance, power, and area.
• Resolve complex, cross-domain design and EDA tool challenges impacting schedule or silicon quality.
• Drive the adoption of advanced techniques through design, verification, validation, and release to production.
• Continuously improve efficiency through automation, scripting, and the integration of AI-driven tools.
• Partner closely with Physical Design, Software, Product Engineering, Validation, and other teams and vendors to resolve complex integration issues and bottlenecks.
• Collaborate with Project Management, Marketing and Application Engineers, Chip Architects, Subsystem Leads, and Verification Teams to deliver complex designs.
• Enhance and grow CBU’s technical capabilities through mentorship, coaching, and recruitment.

What you'll need

• Degree in EE (Bachelor’s or higher).
• Proven leadership skills with strong coaching and mentoring temperament.
• Ability to think both strategically and tactically.
• Deep understanding of all phases of silicon development with expertise in RTL design and verification.
• Strong understanding of functional verification flows and environments.
• Proven success delivering multiple complex tape-outs in high-performance silicon.
• Deep hands-on experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis along with physical design interactions.
• Solid experience with low-power design methodologies and flows.
• Working knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.

Nice to have

• 14+ years of experience.
• Experience with Synopsys or Cadence tools for synthesis, verification or STA.
• Experience with 28nm and smaller silicon process technologies.
• Hands-on experience with ASIC EDA tools/environment.

Details

• Location: Bangalore, India.
• Travel time: 0% - 25%.