ASIC Engineer | RTL Design, Verilog, System Verilog | CDC, Lint | Exp - 8 to 10 years | Bangalore

Overview

Lead ASIC design work on Cisco SiliconOne, covering RTL design through tape-out and lab validation for high-performance, high-volume chips.

What you'll do

• Work on the architecture of complex ASICs, understanding it in depth and identifying problems and solutions.
• Carry out all aspects of implementation: specification, design, timing analysis, power optimization and flow automation.
• Optimize logic for low power and area, and highlight issues and standard methodologies for power and area optimization.
• Document and improve standard methodologies to make the product successful.

What you'll need

• BS/MS with 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC RTL development.
• Hands-on experience with Verilog, SystemVerilog, VCS, Spyglass, CDC and formal verification.
• Experience in system debug, SW/HW bringup and system validation of silicon towards FCS.
• Gate-level understanding of RTL and synthesis.
• Programming/scripting skills in C, C++ and Perl.
• Experience with hardware emulation platforms and tools such as EVE and Veloce.
• Good written/verbal interpersonal skills and leadership skills.

Nice to have

• Worked in architecture and definition of high-scale, high-performance ASICs.
• Validated experience in implementation: specification, RTL design, lint, CDC, timing analysis, formal verification and system testing.
• Validated experience in flow automation (scripting, Makefiles, etc.) and establishing guidelines for the team.
• Good interpersonal skills and validated leadership to accurately describe issues/improvements and lead the team for on-time completion.

Details

• Location: Bangalore, India.