IP RTL Senior Design Engineer

Overview

Develop high-quality IP logic and RTL for Unified Intel Chassis designs, owning secured access control, RAS fault handling, and telemetry/debug observability for the fabric.

What you'll do

• Work closely with architects to define and design complex protocol bridges.
• Define and implement range-based access control for secured memory and register paths across HBW and LBW.
• Own privilege qualification and policy propagation across AXI-Lite, APB, IOSF-SB, and HBW request paths.
• Design and validate parity/ECC generation and checking for request, response, and data channels.
• Define fault behavior for unauthorized accesses and corrupt transactions, including silent block semantics, RAZWI-style handling, poison propagation, and timeout cleanup.
• Build or integrate logging, interrupt, and firmware-visible error harvesting flows for local and global RAS handling.
• Support error injection, diagnostics, and post-silicon debug hooks for security and reliability validation.
• Define and implement telemetry capture for fabric load, latency, congestion, error context, and other operational health indicators.
• Own debug and trace data paths for wrapper-level and fabric-level observability, including data capture, transport, formatting, and handoff to downstream debug infrastructure.
• Design counters, sticky status, snapshots, and firmware-visible CSRs that make performance and failure analysis practical.
• Integrate trigger, monitor, and logging hooks needed for bring-up, stress triage, and post-silicon correlation.
• Work with architecture, validation, firmware, and post-silicon teams to ensure telemetry and debug signals are useful, stable, and diagnosable.
• Balance observability depth against area, timing, bandwidth, and survivability constraints.
• Support root-cause analysis of bandwidth loss, latency outliers, protocol stalls, and intermittent field or lab issues using hardware observability features.
• Develop logic designs, RTL coding, and simulations required for IP blocks, functional units, and subsystems.
• Define architecture and microarchitecture features for the IP block being designed.
• Apply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.
• Support SoC customers with seamless integration and verification of IP blocks.
• Drive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.

What you'll need

• Bachelor's degree in electrical engineering, computer engineering, or related field.
• A minimum of 8 years of experience in logic design and RTL development.
• Proficiency in hardware description languages such as Verilog and SystemVerilog.
• Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
• Experience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).
• Knowledge of IP block integration workflows within SoC designs.
• Expertise in RAS/debug/security/telemetry.
• Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.
• Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.
• Experience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.

Nice to have

• Master's or PhD degree in electrical engineering, computer engineering, or related field.
• 10+ years of professional experience encompassing complex IP logic design for high-performance applications.
• Demonstrated expertise in architecture and microarchitecture definition.
• Familiarity with advanced verification methodologies such as UVM or formal verification techniques.
• Strong communication and collaboration skills, with a proven ability to work effectively in cross-functional teams.
• A mindset for continuous learning and improvement, with an eagerness to tackle challenging, innovative design projects.

Details

• Location: India, Bangalore.
• Work model: on-site presence required.
• Shift: Shift 1 (India).
• Job type: Experienced Hire.