IP Micro-architect (RTL) design Engineer

Overview

Hands-on technical leader driving custom Infrastructure IPs from architecture and microarchitecture definition through RTL implementation and production silicon, while mentoring engineers and influencing architecture decisions.

What you'll do

• Drive architecture and microarchitecture definition of complex custom Infrastructure IPs.
• Develop detailed microarchitecture specifications including datapath design, control logic, packet formats, flow control, ordering rules, coherency mechanisms, and state machines.
• Lead RTL development and collaborate closely with verification, physical design, firmware, and SoC integration teams.
• Evaluate and optimize architecture trade-offs across performance, power, area, scalability, latency, and implementation complexity.
• Design and develop high-performance interconnect, memory, and protocol-centric IP solutions.
• Drive design reviews, microarchitecture reviews, and technical decision-making across multiple projects.
• Support verification planning, debug, emulation, FPGA validation, and silicon bring-up activities.
• Ensure RTL quality through lint, CDC/RDC, synthesis, and design signoff methodologies.
• Mentor junior engineers and provide technical leadership within the IP development team.
• Stay abreast of emerging technologies in AI infrastructure, scale-up fabrics, memory systems, and high-speed interconnects.

What you'll need

• 8-15 years of experience in SoC/IP architecture, microarchitecture, and RTL design.
• Proven experience defining and delivering complex custom IPs from concept through production silicon.
• Strong experience in architecture and microarchitecture development of one or more of the following: Infrastructure IPs, NoC, interconnect fabrics, memory subsystem IPs, cache coherency solutions, or high-speed interface IPs.
• Strong understanding of computer architecture, SoC architecture, digital design methodologies, performance modeling and analysis, synchronization and flow control mechanisms, and high-performance data movement architectures.
• Hands-on RTL design experience using Verilog/SystemVerilog.
• Experience with design signoff methodologies including lint, CDC/RDC, synthesis, and timing closure fundamentals.
• Strong debugging, analytical, and problem-solving skills.
• Excellent verbal and written communication skills.
• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
• Minimum: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience, OR Master's degree in the same fields and 3+ years of Hardware Engineering or related work experience, OR PhD in the same fields and 2+ years of Hardware Engineering or related work experience.

Nice to have

• Experience building custom protocol-based IPs from ground-up architecture through silicon validation.
• Familiarity with AI, Datacenter, Compute, Automotive, Mobile, or XR SoC architectures.
• Experience with ASIC design and implementation flows.
• Knowledge of scripting and automation using Python, Perl, or Tcl.
• Experience with Git, ClearCase, or similar version control systems.
• Exposure to post-silicon debug and bring-up.

Details

• Location: Bangalore, India.
• Core domains include infrastructure IP, NoC, PCIe, CXL, memory systems, cache coherency, UALink, ESUN, and AI scale-up interconnect fabrics.