Chassis IP Senior Design Engineer

Overview

Logic design engineer role in the Intel Chassis Group, delivering logic design of component and foundation IPs used to build SoC chassis.

What you'll do

• Develop logic designs, register transfer level (RTL) coding, and simulations required for functional units, IP blocks, and subsystems.
• Define and implement architecture and microarchitecture features for the interconnect IP block and sub-system, including high-performance data plane and control plane routers, switches, arbiters, protocol conversion bridges, debug/trace components, and clock and power controls.
• Perform rigorous quality checks and optimization of RTL designs to improve IP power, performance, area, and timing, ensuring delivery of high-quality IP.
• Evaluate design trade-offs across area, bandwidth, timing, and reliability to achieve balanced and efficient IP functionality.
• Support Sub-system/SoC customers with high-quality IP integration and verification workflows.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with a minimum of 10 years of experience in logic design and RTL development.
• Proficiency in Verilog/System Verilog and RTL coding.
• Expertise in AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols.
• Experience with Lint/CDC/RDC tools and methodologies.
• Strong understanding of power, performance, timing and area optimization strategies in complex designs.

Nice to have

• 5+ years of experience designing network components such as routers, switches, arbiters, or protocol conversion bridges.
• Knowledge of debug/trace networks, flow control, and hashing methodologies.
• Experience working with leading-edge semiconductor nodes.
• Background in DVFS (Dynamic Voltage Frequency Scaling) and UPF (Unified Power Format).
• Understanding of RAS (Reliability, Availability, and Serviceability) features.
• Proven ability to collaborate across geographically distributed teams and adapt to multi-time zone working environments.
• Familiarity with coherency concepts and memory subsystems.

Details

• Location: India, Bangalore.
• Work model: hybrid, splitting time between on-site at the assigned Intel site and off-site.
• Shift: Shift 1 (India).
• Job type: Experienced Hire.