Lead Principal Engineer - Digital Design

Overview

Lead the architecture, design, and delivery of complex digital IP, ASIC, and SoC solutions, driving key technical initiatives and major subsystem developments, and providing technical leadership and mentorship to engineers.

What you'll do

• Lead architecture, micro architecture, and RTL design of complex digital subsystems, IPs, and SoCs.
• Drive end-to-end design execution from concept, specification, and implementation through silicon bring-up and production.
• Make key technical decisions and trade-offs to optimize performance, power, area, quality, and scalability.
• Collaborate with architecture, verification, physical design, firmware, software, and validation teams to ensure successful product delivery.
• Establish and drive adoption of digital design methodologies, quality standards, and engineering best practices.
• Lead technical reviews, design sign-offs, risk assessments, and root-cause analysis for complex issues.
• Drive innovation, technology roadmap planning, and development of next-generation solutions.
• Contribute to patents, technical publications, and strategic technology initiatives.
• Provide technical leadership, mentor engineers, and influence design decisions that impact product success.

What you'll need

• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 12+ years of industry experience in digital IC design and semiconductor product development.
• Extensive experience in architecture, microarchitecture, RTL design, and SoC/IP development.
• Proven success delivering complex semiconductor products from architecture definition through silicon validation and production.
• Expert-level proficiency in Verilog/System Verilog and modern ASIC/SoC development flows.
• Strong understanding of performance, power, and area (PPA) optimisation.
• Strong understanding of clocking and reset architectures.
• Strong understanding of Design-for-Test (DFT).
• Strong understanding of low-power design methodologies.
• Strong understanding of timing closure and physical design considerations.
• Strong understanding of semiconductor development and productization processes.
• Experience leading technical reviews, design sign-offs, risk assessments, and root-cause investigations.
• Strong stakeholder management, communication, and collaboration skills.

Details

• Location: Bangalore BTP.