Principal Engineer Design-Synthesis, LEC & CLP

Overview

Lead RTL-to-GDS front-end implementation for complex SoC designs, with a focus on synthesis, logic equivalence checking, and low-power verification.

What you'll do

• Develop and maintain front-end design flows and automation frameworks.
• Drive synthesis convergence and design optimization across advanced technology nodes.
• Perform design bring-up, debugging, and issue resolution throughout implementation.
• Execute and close logic equivalence checking and low-power verification activities.
• Collaborate with RTL, STA, DFT, and Physical Design teams on design integration.
• Develop reusable methodologies and automation solutions.
• Support design signoff and project quality goals.

What you'll need

• 10+ years of RTL-to-GDS front-end implementation experience for complex SoC designs.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field.
• Hands-on experience with synthesis, LEC, and low-power verification.
• Experience with Cadence Genus, Conformal LEC/CLP, Synopsys Design Compiler/Fusion Compiler, and Formality.
• Knowledge of MCMM, UPF/CPF, timing constraints, and power intent verification.
• Strong Tcl, Python, and/or Perl programming and automation skills.
• Experience working with STA, DFT, Physical Design, and RTL teams through tape-out.

Details

• Location: Bangalore, India.