LOCATION

Bangalore · Hybrid

EXPERIENCE

13+ Years

SALARY

Negotiable

SKILLS REQUIRED

Timing ClosureStatic Timing AnalysisSDC ConstraintsTCL AutomationCadence TempusMulti-Mode Timing

Job description

Overview

Lead timing closure, constraints validation, and timing sign-off for complex, multi-million-gate SoCs across block-level and full-chip designs.

What you'll do

Drive MMMC timing closure from block implementation through full-chip integration.
Fix setup, hold, transition, crosstalk, and signal-integrity violations using ECOs and optimization tools.
Build and execute multi-signoff STA environments with PrimeTime and Cadence Tempus.
Generate and maintain SDC constraints across block/IP and full-chip levels.
Validate timing across Scan, At-Speed, MBIST, and LBIST modes.
Collaborate with DFT, RTL, and P&R teams on timing, CDC/RDC, CTS, and routing issues.
Develop Tcl, Python, or Perl automation for timing analysis and regression.

What you'll need

Minimum 13 years of experience in full-chip STA.
Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.
Expertise with Synopsys PrimeTime/PT-PX, Cadence Tempus, PrimeClosure, and Tweaker.
Experience with constraints verification tools including Synopsys TCM, SpyGlass Constraints, or Cadence CCD.
Hands-on experience with UPF constraints and low-power design architectures.
Understanding of POCV/LVF, temperature inversion, crosstalk/noise analysis, DFT, and hierarchical clock networks.
Expert Tcl skills, plus Python or Perl for automation and constraint auditing.

Details