SoC Clocking Specialist (Physical Design)

Overview

Lead the clock architecture and physical implementation of next-generation edge AI hardware, bridging frontend logic and backend execution to deliver a robust, power-efficient clock tree on advanced technology nodes.

What you'll do

• Collaborate closely with the SoC Architecture and RTL teams to define optimal clocking schemes, clock gating strategies, and synchronous/asynchronous boundaries.
• Own the end-to-end Clock Tree Synthesis (CTS) strategy, working alongside the Physical Design and Static Timing Analysis (STA) teams to drive timing closure, minimize skew, and optimize insertion delay.
• Run detailed SPICE simulations (using HSPICE, CustomSim, etc.) on critical clock paths to model and analyze jitter, duty cycle distortion, slew degradation, and local on-chip variation (OCV).
• Architect custom clock distribution networks (trees, meshes, or hybrid topologies) that meet stringent high-frequency requirements while strictly managing dynamic power.
• Integrate and validate high-speed clocking IPs (PLLs, DLLs, oscillators) into the top-level SoC clock network.
• Establish and refine CTS and SPICE analysis methodologies to ensure silicon predictability from RTL to GDSII.

What you'll need

• Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a related field.
• 8+ years of experience in semiconductor physical design, with a strong focus on clocking architecture and implementation.
• Deep understanding of high-performance clock tree methodologies across advanced process nodes.
• Proven hands-on experience running and analyzing SPICE simulations for clock networks.
• Thorough understanding of STA constraints, jitter budgeting, cross-talk, and variation modeling.
• Strong command over industry-standard EDA tools for physical design and timing (e.g., Synopsys ICC2/PrimeTime or Cadence Innovus/Tempus) and circuit simulation.
• Exceptional communication skills with a proven ability to align cross-functional teams (Frontend, Design Verification, PD, and Sign-off) around complex technical solutions.
• Proficiency in Python, Tcl, or Perl to automate flows and analyze large timing datasets.

Details

• Location: Bengaluru, India.
• Role type: Full-time.