DDR STA/Timing Engineer, Lead

Overview

Lead the STA and timing work for multi-mode, multi-voltage domain designs as a Hardware Engineer in Qualcomm's Hardware Engineering group.

What you'll do

• Set up, converge, review and sign off STA for multi-mode, multi-voltage domain designs.
• Analyze, validate and debug timing across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
• Evaluate multiple timing methodologies and tools on different designs and technology nodes.
• Develop automation scripts within STA/PD tools for methodology development.
• Work in a cross-collaborative environment and communicate technical content clearly in writing.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience, OR Master's degree in the same fields and 1+ year of Hardware Engineering or related work experience, OR PhD in the same fields.
• Education: B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.
• Experience in design automation using TCL/Perl/Python.
• Familiarity with digital flow design implementation from RTL to GDS: ICC, Innovus, PT/Tempus.
• Familiarity with process technology enablement: circuit simulations using Hspice/FineSim, Monte Carlo.
• Good technical writing and communication skills.

Nice to have

• 5+ years of experience in STA/Timing.
• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, latch transparency handling, 0-cycle and multi-cycle path handling.
• Hands-on experience with STA tools Prime-time and Tempus.
• Experience driving timing convergence at Chip-level and Hard-Macro level.
• In-depth knowledge of cross-talk noise, signal integrity, layout parasitic extraction, and feed-through handling.
• Knowledge of ASIC back-end design flows and tools (ICC2, Innovus).
• Knowledge of Spice simulation (Hspice/FineSim, Monte Carlo) and silicon to spice model correlation.
• Proficiency in scripting languages TCL, Perl, Awk.
• Basic knowledge of device physics.