NPU STA/Timing Engineer

Overview

Hardware engineering role focused on static timing analysis (STA) and timing signoff for multi-mode, multi-voltage domain designs, including STA flow optimization and automation.

What you'll do

• Perform STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
• Carry out timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.
• Develop automation scripts within STA/PD tools for methodology development.
• Collaborate in a cross-functional environment and communicate technical content clearly in writing.
• Work on design automation using TCL/Perl/Python.
• Work on digital flow design implementation from RTL to GDS using ICC, Innovus, PT/Tempus.
• Work on process technology enablement, including circuit simulations using Hspice/FineSim and Monte Carlo.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.
• Good technical writing and communication skills; willingness to work in a cross-collaborative environment.
• Experience in design automation using TCL/Perl/Python.
• Familiarity with digital flow design implementation RTL to GDS: ICC, Innovus, PT/Tempus.
• Familiarity with process technology enablement: circuit simulations using Hspice/FineSim, Monte Carlo.

Nice to have

• 5 - 10 years of experience in STA/Timing.
• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, latch transparency handling, 0-cycle and multi-cycle path handling.
• Hands-on experience with STA tools: Prime-time, Tempus.
• Experience driving timing convergence at Chip-level and Hard-Macro level.
• In-depth knowledge of cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed-through handling.
• Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
• Knowledge of Spice simulation Hspice/FineSim, Monte Carlo; silicon to spice model correlation.
• Proficiency in scripting languages: TCL, Perl, Awk.
• Basic knowledge of device physics.

Details

• Location: Bangalore, India.