DDR STA/Timing Engineer (Staff/ Senior Staff)

Overview

DDR STA/Timing Engineer responsible for setting up and optimizing STA flows for multi-mode, multi-voltage designs, including timing analysis, validation, and debug across PVT conditions.

What you'll do

• Set up STA, perform convergence, run reviews, and sign off multi-mode and multi-voltage domain designs.
• Conduct timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus.
• Run PrimeTime and/or Tempus for STA flow optimization and Spice-to-STA correlation.
• Evaluate multiple timing methodologies/tools across designs and technology nodes.
• Develop automation scripts within STA/PD tools for methodology development.
• Work on design automation using TCL/Perl/Python.

What you'll need

• Minimum bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field or equivalent as listed.
• 2+ years of hardware engineering or related work experience (or 1+ year with a master’s, as listed).
• Experience in design automation using TCL/Perl/Python.
• Knowledge of digital flow design implementation RTL to GDS using ICC, Innovous, PT/Tempus.
• Experience with circuit simulations using Hspice/FineSim and Monte Carlo.
• Good technical writing and communication skills for cross-collaborative work.

Details

• Location: Bangalore, India.