GPU STA/Timing Engineer (Senior Lead/Staff)

Overview

GPU STA/Timing engineer role driving timing signoff and closure for next-generation high-performance GPU designs.

What you'll do

• Own block-level and full-chip STA signoff for GPU designs.
• Develop and validate timing constraints using SDC.
• Run MCMM/MMMC timing analysis, perform timing closure, and implement ECOs.
• Drive setup/hold, noise, SI, and low-power timing closure.
• Collaborate with cross-functional teams to resolve timing issues.
• Enhance STA methodologies, signoff flows, and automation, and mentor junior engineers.

What you'll need

• BS/MS in Electrical/Electronics Engineering or a related field.
• 6-10 years of experience in ASIC/SoC STA and timing signoff.
• Strong expertise in STA, MCMM/MMMC, SDC, timing closure, and ECOs.
• Hands-on experience with Synopsys PrimeTime.
• Proficiency in Tcl/Python scripting.
• Strong understanding of physical design concepts and implementation flows.

Details

• Location: Bangalore, India.