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NPU Physical Design Engineer

Qualcomm
NewPosted today

LOCATION

Bangalore · Onsite

EXPERIENCE

2+ Years

SKILLS REQUIRED

Place and routeTiming ClosurePhysical VerificationClock Tree SynthesisStatic Timing Analysis

Job description

Overview

Implement place-and-route (PNR) for the Qualcomm Hexagon NPU, owning the full physical implementation flow and signoff on latest technology nodes.

What you'll do

  • Take complete ownership of PNR implementation, including floorplanning, placement, clock tree synthesis (CTS), and post-route optimization on latest nodes.
  • Carry out signoff work including STA, power analysis, formal verification (FV), low power verification and physical verification (PV).

What you'll need

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience, OR Master's degree in a related field and 3+ years of Hardware Engineering or related work experience, OR PhD in a related field and 2+ years of Hardware Engineering or related work experience.
  • Good hands-on experience with floorplanning, PNR and STA flows.
  • Good knowledge of placement and clock tree synthesis (CTS), optimization, etc.
  • Good understanding of signoff domains, including LEC/CLP/PDN knowledge.
  • Good knowledge of Unix/Linux and Perl/TCL fundamentals and scripting.
  • 2+ years of experience with PNR flow in latest technology nodes (e.g., 4nm/5nm/7nm/10nm).
  • Quick learner with good analytical and problem-solving skills.

Details

  • Location: Bangalore, India.

Read the full description and apply on the company’s own careers page.

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NPU Physical Design Engineer