Lead Logic Design - PCIE IP/Subsystem Engineer

Overview

Lead Logic Design Engineer to lead micro-architecture and RTL design for complex connectivity IPs/subsystems, covering architecture through silicon bring-up.

What you'll do

• Develop RTL and micro-architecture for complex connectivity IPs/subsystems.
• Translate specifications and system requirements into hardware architecture.
• Design scalable, high-performance logic for controllers and subsystems.
• Work across Transaction, Data Link, and Physical interface integration layers as applicable.
• Develop and review RTL using SystemVerilog/Verilog.
• Drive optimization across performance, latency, area, and power.
• Support post-silicon debug and root-cause analysis.

What you'll need

• 6-10 years of experience.
• Extensive experience in complex connectivity IPs such as PCIe, UALink, Ethernet, CXL, or UCIe.
• Strong RTL design experience using SystemVerilog/Verilog.
• Deep knowledge of PCIe architecture and protocol.
• Experience with simulation, lint, CDC, synthesis, and timing considerations.
• Strong debugging and problem-solving skills.

Nice to have

• Experience working in switching silicon.
• Experience working end-to-end from concept to silicon production.

Details

• Location: Bengaluru, Karnataka, India.