Senior FPGA IP Design Engineer

Overview

Own the architecture, micro-architecture and parameterizable RTL design of high-performance soft IP blocks, including advanced AMBA AXI Interconnect IP, with a focus on portability, scalability and timing closure across FPGA architectures.

What you'll do

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces
• Collaborate closely with the verification team to shape test plans and improve verification coverage
• Work with the physical design team to understand and resolve timing, power and congestion challenges
• Work with the verification team on regression failure debug and root cause, and provide RTL fixes if necessary
• Provide technical support to the FAE team on pre-sales customer engagements
• Provide technical support to the AE team on post-sales customer deliveries
• Apply working knowledge of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis within the design flow
• Develop RTL micro-architecture from scratch
• Provide technical guidance and mentorship to other engineers while remaining a hands-on individual contributor

What you'll need

• Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
• 5+ years of dedicated RTL/FPGA design experience
• Deep, hands-on knowledge of the AMBA AXI4 protocol suite and high-speed memory interfaces
• Proficiency with FPGA implementation tools and EDA simulation software (Siemens Questa/Modelsim, Synopsys VCS)
• Strong scripting skills in Python, Tcl or Perl for build automation and test automation

Details

• Job type: Regular
• Shift: Shift 1 (India)
• Location: Bengaluru, Karnataka, India