Senior SOC Design Engineer - Networking Group

Overview

NVIDIA is hiring a Senior SOC Design and Integration Engineer for the Networking chip design group, working on next-generation DPUs and Switch Silicon chips in a new, fast-growing India team.

What you'll do

• Understand all features of a given project and define project milestones based on internal roadmaps, assign them, and track them through an agile framework.
• Define and develop system-level methodologies, tools, and IPs to build subsystems in an efficient and scalable manner.
• Work with the SOC Assembly team and drive cross-functional teams toward SOC milestone execution.
• Integrate all the pieces for a defined project milestone and deliver the model to relevant teams for verification at cluster, sub-system, SOC and emulation levels.

What you'll need

• BS (or equivalent experience) / MS with 3+ years of practical semiconductor design and architecture experience building complex SoCs.
• Must have firsthand experience and solid understanding of all phases of SOC development across multiple ASIC projects, including ASIC architecture, micro-architecture, RTL design, verification, timing closure and physical design.
• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools such as Indago, GDB, etc.).
• Experience working with software teams to tightly define the HW/SW interface, including control/status registers, interrupt and error handling.
• Hands-on experience with successful tape-outs of multiple sophisticated, high-volume SoCs in advanced process nodes.
• Exposure to various chip design functions to collaborate and tackle sophisticated cross-functional problems.
• Excellent verbal and written communication skills to interact with cross-functional teams and build consensus.

Nice to have

• C/C++ programming, Python, or other industry-standard scripting language experience.
• Experience in synthesis, physical design and DFT.
• Experience in RTL build and design automation.
• Chip lead type of technical leadership experience delivering complex SOCs for enterprise and/or HPC applications.
• Experience in RTL coding and debug, and performance/power/area analysis and trade-offs.
• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.
• Prior experience with smartNIC and/or high-speed interconnects.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.

Details

• Location: Bengaluru, India.
• Work mode: Hybrid.