Principal Digital Design Engineer

Overview

Principal Digital Design Engineer designing, developing, and optimizing digital logic circuits and systems across the full ASIC/FPGA design cycle.

What you'll do

• Design and develop RTL code using Verilog/SystemVerilog/VHDL.
• Architect and implement complex digital blocks and subsystems.
• Perform functional verification using simulation and UVM/OVM methodologies.
• Develop testbenches and execute validation plans.
• Run synthesis, timing analysis, and area optimization.
• Debug issues across RTL, gate, and silicon levels and support post-silicon bring-up.

What you'll need

• Typically 10+ years of experience in digital design or ASIC/FPGA development.
• Strong proficiency in Verilog/SystemVerilog/VHDL.
• Experience with RTL design and simulation tools (ModelSim, VCS, Xcelium).
• Experience with synthesis tools (Design Compiler, Genus).
• Static Timing Analysis using PrimeTime.
• Education in Electronics Engineering/Electrical Engineering/VLSI Design/Computer Engineering.

Details

• Location: Noida.