Principal CAD Engineer Digital Verification

Overview

Principal CAD Engineer specializing in Digital Verification for ASIC/SoC development. You’ll build and support verification regression/automation infrastructure and enable DV teams with CAD tools and methodologies.

What you'll do

• Troubleshoot simulation, regression, coverage, and debug flow issues for Design & Verification teams.
• Identify DV bottlenecks and provide practical solutions or workarounds.
• Deploy and maintain CAD tools, scripts, and environments for digital verification flows.
• Provide day-to-day support for EDA tools including VCS, Xcelium, Verdi, and vManager.
• Support regression and CI/CD systems with stable execution and timely issue resolution.
• Monitor and optimize infrastructure usage such as compute farms and LSF environments.

What you'll need

• 12+ years of experience in Digital Verification / CAD / engineering support-related roles.
• Strong understanding of digital verification flow across simulation, regression, coverage, and debug.
• Hands-on experience with SystemVerilog and UVM from a debugging/support perspective.
• Proficiency in scripting/programming, e.g., Python, Tcl, Perl, or similar.
• Experience in Linux-based environments.
• Experience with EDA tools such as VCS, Xcelium, Verdi, and vManager.
• Exposure to regression environments, CI/CD systems, and compute farm usage.

Details

• Location: Noida.