DV Power Vectors & Window Extraction Engineer (Staff/Sr Staff)

Overview

Develop and execute Design Verification power vectors and extract power-analysis windows across simulation, emulation, and silicon-validation environments.

What you'll do

• Develop and execute DV power vectors covering key workloads, power states, transitions, boot flows, retention, reset, and stress scenarios.
• Bring up and maintain simulation, emulation, and power-aware verification environments.
• Analyze waveforms, activity dumps, power reports, and execution logs to identify meaningful power-analysis windows.
• Extract and document windows for peak power, average power, dynamic voltage drop, thermal analysis, and pre-silicon/post-silicon correlation.
• Debug vector failures, power-state sequencing issues, missing activity, waveform mismatches, and unexpected power behavior.
• Collaborate closely with DV, Design, Power, Physical Design, Emulation, PTE, and Post-Silicon teams.
• Maintain traceability between test cases, configurations, waveforms, extracted windows, and delivered vector collateral.

What you'll need

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• 7-15 years of experience in Design Verification, power-aware verification, vector development, or power analysis.
• Strong understanding of RTL simulation and waveform analysis.
• Strong understanding of SystemVerilog/UVM or equivalent verification environments.
• Strong understanding of low-power concepts, power states, clock gating, retention, and isolation.
• Strong understanding of simulation, emulation, GLS, or silicon-validation flows.
• Strong understanding of power estimation and activity analysis.
• Proficiency with scripting languages such as Python, Perl, Shell, or Tcl.
• Experience using waveform-debug and power-analysis tools.
• Ability to identify representative, peak, and corner-case power windows.
• Strong debugging, analytical, documentation, and communication skills.
• Experience working across multiple engineering teams in a fast-paced environment.

Nice to have

• Experience with UPF and power-intent verification.
• Knowledge of CPU, SoC, memory, interconnect, or subsystem power behavior.
• Experience with dynamic voltage drop, IR-drop, VMIN, or thermal analysis.
• Familiarity with emulation platforms and large-scale workload execution.
• Experience correlating pre-silicon power results with post-silicon measurements.
• Understanding of frequency-voltage operating points and power-performance tradeoffs.

Details

• Location: Bangalore, India.