Engineer II - Verification

Overview

Verification Engineer in the Secure Computing Products (SCG) Group, part of a digital logic design effort building hardware embedded controller solutions.

What you'll do

• Own the verification of complex blocks and subsystems within ARM-based SoCs.
• Perform digital design verification at the block level and chip-level functional verification.
• Define test plans from design specifications, implement constrained-random and directed tests, and drive coverage closure.
• Develop test environments using SystemVerilog and UVM verification methodologies.
• Integrate with RTL and carry out basic simulation bring-up for the design.
• Create multiple test cases per test plan and launch regressions.
• Generate code and functional coverage, analyze coverage results and correlate them with the test plan.
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design teams to resolve bugs.
• Contribute to AI/automation initiatives for regression management, coverage tracking, and debug automation.
• Work with architects and validation engineers to ensure end-to-end feature completeness and quality.
• Provide technical guidance and mentorship to junior engineers as required.
• Continuously improve verification methodology, reuse, and efficiency.

What you'll need

• Bachelor's or Master's degree in Electrical/Electronic Engineering or a related field, with 2–4 years of experience in ASIC/SoC functional verification.
• Strong expertise in SystemVerilog and UVM methodology.
• Hands-on experience developing block, subsystem and SoC-level verification environments.
• Solid understanding of AMBA, USB, I2C, SPI and eSPI protocols.
• Good understanding of digital design, RTL fundamentals, and simulation/debug flows.
• Familiarity with scripting (Python/TCL/Perl) for automation.
• Good programming skills in languages such as C and C++.
• Excellent communication, teamwork, problem-solving, strong analytical and debugging skills.
• Highly motivated, detail-oriented, and committed to delivering quality results.
• Ability to lead cross-site teams and manage complex design programs.

Nice to have

• Experience with Cadence, Synopsys or Mentor verification platforms.
• Exposure to AI/ML-based verification, emulation, or acceleration.

Details

• Location: Chennai, India.
• Travel: 0% to 25%.