Engineer II - Verification

Overview

Verification Engineer in the Microcontroller (MCU) Business Unit, part of a digital design effort delivering low-power embedded MCU solutions, covering verification of MCU subsystems and full-chip SoCs built around ARM Cortex-M0+, RISC-V and other cores, from verification planning through tape-out.

What you'll do

• Own the verification of complex blocks, subsystems and full-chip designs within MCU SoCs based on ARM Cortex-M0+ and RISC-V.
• Define test plans from design specifications, implement constrained-random and directed tests at block, subsystem and chip level, and drive functional, code and assertion coverage closure.
• Own IP-based verification and sign-off for MCU IPs and peripherals, including IP-level test plans, reusable test benches and VIP, regression and coverage closure, and formal sign-off checklists before IP delivery for SoC integration.
• Develop and maintain SystemVerilog/UVM-based verification environments, including agents, scoreboards, checkers and assertions for AHB and APB bus protocols.
• Verify MCU peripherals such as ADC, Analog Comparator (AC), TWI (I2C), SPI and USART, along with timers, GPIO and DMA.
• Develop C-based firmware and directed tests running on the processor core for chip-level verification and bring-up.
• Perform mixed-signal co-simulations to verify analog/digital integration (e.g., ADC, AC, oscillators, regulators, POR).
• Run and debug gate-level simulations (GLS) and power-aware (UPF) simulations to verify power domains, isolation, retention and low-power modes.
• Support verification of clock, reset and power management, including CDC/RDC checks.
• Create test cases as per the test plan, launch and manage regressions, and analyze code/functional coverage and correlate it with the test plan.
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design, firmware and validation teams to resolve bugs.
• Leverage the latest AI/ML tools and LLM-based assistants to improve RTL verification productivity, including writing effective prompts to generate test bench code, stimulus, assertions, scripts and documentation.
• Apply AI-driven techniques for log analysis, waveform triage, failure clustering, root cause analysis, regression management and coverage tracking to improve debug efficiency.
• Design, run and analyze AI-assisted trials and experiments to improve verification productivity and quality, and integrate AI tools with existing EDA flows and scripts.
• Work with architects, design and validation engineers to ensure end-to-end feature completeness and quality.
• Provide technical guidance and mentorship to junior engineers as required.
• Continuously improve verification methodology, reuse and efficiency.

What you'll need

• Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field, with 2–5 years of experience in MCU/ASIC/SoC functional verification.
• Strong expertise in SystemVerilog and C.
• Hands-on experience in developing block/subsystem/SoC-level verification environments.
• Working knowledge of embedded processor cores, ARM Cortex-M0+ and/or RISC-V, and their integration and verification in MCU SoCs.
• Solid understanding of AMBA AHB and APB bus protocols.
• Hands-on experience verifying MCU peripherals such as ADC, AC, TWI (I2C), SPI and USART.
• Good programming skills in C (embedded/firmware tests) and SystemVerilog.
• Experience in IP-based verification and sign-off, including IP-level test plans, reusable verification components, coverage closure and sign-off criteria.
• Experience in mixed-signal co-simulation (analog/digital, real-number or Verilog-AMS models).
• Hands-on experience running and debugging gate-level simulations (GLS) and UPF/power-aware simulations.
• Good understanding of Digital Design, RTL fundamentals, clock/reset/power concepts, CDC/RDC, and simulation/debug flows.
• Familiarity with scripting (Python/TCL/Perl) for automation.
• Excellent written and verbal communication, teamwork, problem-solving abilities, and strong analytical and debugging skills.
• Up-to-date knowledge of AI/ML tools; ability to use and prompt LLM-based assistants to generate code, stimulus, documentation, root cause analysis and scripts.
• Ability to apply AI-driven techniques for log analysis, waveform triage and failure clustering, and to design, run and analyze AI-assisted trials to improve productivity or quality.
• Know-how of integrating AI tools with existing EDA flows and scripts.
• Ability to collaborate effectively across global, cross-functional teams in a fast-paced, evolving MCU product environment.

Nice to have

• UVM experience.
• Exposure to USB.
• C++ programming.
• Experience working with Cadence, Synopsys or Mentor verification platforms.

Details

• Location: Chennai, India.
• No travel.