FPGA SW Validation Engineer (PR)

Overview

Validate FPGA compiler optimizations, Partial Reconfiguration (PR) flow and debug features using Quartus and Altera FPGA hardware, and help resolve customer issues.

What you'll do

• Validate and research compiler optimizations, the Partial Reconfiguration (PR) flow, and debug features such as SignalTap and System Console, using Quartus Design Software and Altera FPGA hardware.
• Create designs using HDLs and Altera IPs, and verify them for functionality and timing on Altera FPGA hardware boards.
• Regress designs during each release for QoR, and monitor performance over the targeted FPGA devkits to assess improvements.
• Collaborate with cross-functional teams to develop and improve validation strategies for Compiler/PR validation, and help resolve customer issues as they occur.

What you'll need

• Minimum 6+ years of relevant experience in FPGA/ASIC design, RTL coding, verification and HW debug.
• Master's or Bachelor's degree in Electronics/VLSI/Digital Design or other related disciplines.
• FPGA/digital logic design and RTL/HDL design and verification using VHDL, Verilog or SystemVerilog.
• Experience with FPGA devices such as Agilex and Virtex, and tools such as Altera Quartus, Xilinx Vivado and Synplify.
• Good experience in the FPGA Partial Reconfiguration (PR) flow, and hardware design and debugging using SignalTap or ChipScope.
• Good experience with simulation/verification of digital designs using QuestaSim, VCS or XCelium, STA, and hardware validation of FPGA designs.
• Knowledge of Unix/Linux along with automation using Shell, Perl/TCL or Python scripting.
• Knowledge of PCIe, Ethernet, Avalon bus protocols, AHB, AXI, HPS and high-speed interfaces is essential.

Details

• Location: Bengaluru, Karnataka, India.
• Job type: Regular. Shift: Shift 1 (India).