Layout ASIC Engineer

Overview

Support the physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions. Contribute to physical design from concept through tapeout, primarily through block-level layouts while assisting with top-level integration.

What you'll do

• Support layout development and physical implementation of analog, mixed-signal circuits, high-speed interfaces including SerDes and PAM4, and supporting digital blocks.
• Participate in block-level floorplanning, placement, routing, and integration for complex mixed-signal ICs.
• Collaborate with circuit designers to translate schematics and performance targets into optimized physical layouts.
• Optimize layouts for electrical performance, matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability.
• Ensure compliance with foundry design rules including DRC, LVS, ERC, density, EM/IR, and reliability requirements.
• Assist in integration across analog, digital, and high-speed domains, including top-level assembly of SerDes, PAM4 paths, clocking, and control logic.
• Review post-layout extraction results and support simulation closure.
• Apply best practices for symmetry, shielding, isolation, and signal integrity.
• Partner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration.
• Identify and help resolve layout-related issues affecting performance, yield, or production readiness.
• Participate in layout reviews and provide input on feasibility, tradeoffs, and tapeout risks.
• Collaborate with CAD teams to improve layout flows, automation, and productivity.
• Support tapeout readiness, including database checks and signoff.
• Assist senior engineers with mentoring more junior layout team members and adopt strong layout methodology.
• Support silicon bring-up, debug, and failure analysis for layout-related issues.
• Collaborate with analog/mixed-signal circuit designers, digital designers, verification engineers, package engineers, process technologists, CAD specialists, reliability experts, post-silicon validation teams, architects, designers, and signoff teams.

What you'll need

• Bachelor’s or Master’s degree in Electrical Engineering or an equivalent field.
• 3+ years of layout design experience in analog, mixed-signal, or high-speed IC development.
• 4-6 years of experience in custom IC layout for analog, mixed-signal, and high-speed designs.
• Hands-on experience supporting block-level layout efforts through tapeout.
• Strong skills in custom layout design, physical verification, and parasitic-aware implementation.
• Solid technical skills and a strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity.
• Good knowledge of device-level layout techniques including common-centroid, interdigitation, guard rings, and isolation structures.
• Proficiency with industry-standard tools such as Cadence Virtuoso and Calibre, or equivalent.
• Understanding of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows.
• Experience with Cadence or similar custom layout tools.
• Comfort working in Linux environments.
• Excellent analytical, problem-solving, communication, and teamwork skills.
• Demonstrated ability to contribute effectively and grow as a technical leader in a fast-paced environment.
• Ability to work as a team player with cross-functional teams spread across geo-locations.

Nice to have

• Master’s degree.
• Familiarity with ASIC/SoC tapeout processes.
• Experience with scripting in Python, Perl, or TCL for layout automation.

Details

• Location: Bangalore, India.