MTS - Analog Layout

Overview

Micron Technology is seeking an MTS - Analog Layout engineer to lead full-custom layout for complex analog and mixed-signal IP blocks, owning layout quality from floor-planning through tape-out.

What you'll do

• Lead full-custom layout for complex Analog / Mixed-Signal IP blocks, including bandgap references, LDOs and regulators, charge pumps (positive/negative), PLLs, delay lines, oscillators, IO & PHY-related analog blocks, temperature sensors, bias circuits, and ESD protection devices and clamps.
• Own layout quality from floor-planning to tape-out, ensuring device matching and symmetry, noise isolation and substrate strategies, robust power/ground planning, and yield, reliability, and DFM compliance.
• Work closely with circuit designers to translate performance goals into layout strategies, especially in noise-sensitive mixed-signal environments.
• Apply advanced FinFET node expertise, including fin quantization awareness, multi-Vt and multi-fin strategies, and advanced metal stack planning.
• Apply planar CMOS experience for analog robustness and legacy IP support.
• Use foundry PDKs, layout-dependent effects (LDEs), and process variability knowledge in layout work.
• Drive and close DRC, LVS, ERC, ANTENNA, and reliability checks.
• Review and address EM/IR, latch-up, ESD window compliance, device stress, and matching degradation issues.
• Interface with foundry and CAD teams for waiver management and signoff convergence.
• Provide technical guidance and design reviews for junior and mid-level layout engineers.
• Establish and document best-known methods (BKMs) for AMS layout across nodes.
• Drive IP reuse, layout template development, and methodology improvements.
• Identify high-value AI/ML and Generative AI applications in circuit layout.
• Develop AI-assisted layout and verification solutions using Python/scripting and EDA automation.
• Translate layout expertise into constraints, algorithms, datasets, and measurable optimization objectives.
• Develop, integrate, and validate AI-driven methodologies against traditional designer-driven flows.

What you'll need

• Strong experience in advanced FinFET nodes such as TSMC 3nm and 5nm.
• Solid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm).
• Deep understanding of foundry PDKs, layout-dependent effects (LDEs), and process variability.
• Strong understanding of AI/ML and Generative AI concepts.
• Proficiency in Python/scripting and EDA automation.

Details

• Location: Bengaluru, Karnataka, India.