MTS - Analog Layout

Overview

Lead full-custom layout for complex analog and mixed-signal IP blocks, owning layout quality from floor-planning through tape-out and mentoring junior and mid-level layout engineers.

What you'll do

• Lead full-custom layout for complex Analog / Mixed-Signal IP blocks, including bandgap references, LDOs and regulators, charge pumps (positive/negative), PLLs, delay lines, oscillators, IO and PHY-related analog blocks, temperature sensors, bias circuits, and ESD protection devices and clamps.
• Own layout quality from floor-planning to tape-out, ensuring device matching and symmetry, noise isolation and substrate strategies, robust power/ground planning, and yield, reliability and DFM compliance.
• Work closely with circuit designers to translate performance goals into layout strategies, especially in noise-sensitive mixed-signal environments.
• Apply advanced FinFET node expertise (such as TSMC 3nm and 5nm), including fin quantization awareness, multi-Vt and multi-fin strategies, and advanced metal stack planning.
• Apply planar CMOS technology expertise (such as 40nm, 65nm and 90nm) for analog robustness and legacy IP support.
• Apply deep understanding of foundry PDKs, layout-dependent effects (LDEs), and process variability.
• Drive and close DRC, LVS, ERC, ANTENNA, and reliability checks, and review and address EM/IR, latch-up, ESD window compliance, and device stress and matching degradation issues.
• Interface with foundry and CAD teams for waiver management and signoff convergence.
• Provide technical guidance and design reviews for junior and mid-level layout engineers.
• Establish and document best-known methods (BKMs) for AMS layout across nodes.
• Drive IP reuse, layout template development, and methodology improvements.
• Apply AI/ML and Generative AI concepts to identify high-value applications in circuit layout.
• Use Python/scripting and EDA automation to develop AI-assisted layout and verification solutions.
• Translate layout expertise into constraints, algorithms, datasets, and measurable optimization objectives.
• Develop, integrate, and validate AI-driven methodologies against traditional designer-driven flows.

What you'll need

• Strong experience in advanced FinFET nodes such as TSMC 3nm and 5nm.
• Solid background in planar CMOS technologies (such as 40nm, 65nm and 90nm).
• Deep understanding of foundry PDKs, layout-dependent effects (LDEs), and process variability.
• Strong understanding of AI/ML and Generative AI concepts.
• Proficiency in Python/scripting and EDA automation.

Details

• Location: Bengaluru, India.