Principal Engineer, ASIC Validation

Overview

Principal Engineer role focused on ASIC validation through pre-silicon SoC deployment and emulation on ZEBU, working with design, SoC C, and firmware teams on PCIe, LPDDR and ONFI subsystems.

What you'll do

• Complete hands-on Xilinx FPGA flow, Vivado flow and protocompiler or ZEBU emulation flow.
• Own complete SoC deployment on pre-silicon platforms on ZEBU.
• Work with Design/SoC C/FW teams to identify actual FW implementation and plan and perform validation accordingly.
• Review SoC verification plan for PCIe/LPDDR/ONFI subsystems and create or understand PCIe/LPDDR/ONFI validation plans with SoC C, AE and FW teams.
• Develop understanding of the SoC and perform processor-based SoC prototyping and emulation using C/FW/AE flow.
• Run SoC C-based simulations for test case understanding and debug using VCS.
• Write Verilog RTL when required and debug using Xilinx FPGA Vivado flow.
• Work with overseas teams for PCIe/LP bring-up and debug.

What you'll need

• Bachelor's or Master's degree or equivalent experience in Engineering.
• Minimum 12+ years of processor-based SoC and hands-on ZEBU implementation experience.
• Hands-on ZEBU experience.
• Hands-on experience with Xilinx FPGA debug using Chipscope flow.
• Proficiency in FPGA debug skills.
• Strong root-cause skills across hardware and RTL layers.
• Good understanding of any of PCIe/NVMe/LPDDR/ONFI architecture.
• Strong Verilog coding skills.
• Proven experience in scripting languages such as Python, Perl or TCL.
• Good written and oral communication.
• Positive attitude and well-mannered, mature behavior.

Nice to have

• Hands-on experience with HAPS 100, HAPS 200, ZEBU or Palladium.
• Thorough knowledge of ZEBU or Palladium flow, Xilinx UltraScale FPGA and Vivado flow.
• Leverage AI-enabled tools to improve productivity and decision making.
• Knowledge of industry-standard interfaces such as ONFI, AXI, LPDDR and PCIe.

Details

• Location: Hyderabad, Telangana, India.