Senior Design Engineer - Memory Subsystem

Overview

Work as a Senior Design Engineer on the design of memory sub-system components used in GPUs and SOCs. Make architectural trade-offs based on features, performance requirements and system limitations, develop micro-architecture and RTL, and deliver a fully verified, synthesis/timing clean design.

What you'll do

• Own micro-architecture and RTL development of design modules.
• Micro-architect features to meet performance, power and area requirements.
• Work with HW architects to define critical features.
• Collaborate with verification teams to verify the correctness of implemented features.
• Interact with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
• Co-operate with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
• Work on post-silicon verification and debug.

What you'll need

• BS / MS or equivalent experience.
• 4+ years of design experience.
• Experience in micro-architecture and RTL development of complex designs.
• Exposure to design and verification tools, including VCS or equivalent simulation tools and debug tools like Debussy and GDB.
• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, timing analysis, floor-planning, ECO, bring-up and lab debug.
• Expertise in Verilog.

Nice to have

• Design experience in memory subsystem or network interconnect IP.
• Good debugging and problem solving skills.
• Scripting knowledge in Python, Perl or shell.
• Good interpersonal skills and ability and desire to work as a part of a team.

Details

• Location: Bengaluru, India.