Overview
Design and develop custom IO circuits and support their validation through silicon bring-up, characterization, debugging, and production ramp activities.
What you'll do
- Design custom IO circuits, including GPIO, LVDS, LVCMOS, SSTL, HSTL, DDR interfaces, and SerDes support circuits.
- Perform transistor-level design and simulation using advanced CMOS technology nodes.
- Develop and optimize ESD protection, level shifter, buffer, driver, and on-chip termination circuits.
- Run pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.
- Perform signal integrity analysis, including IBIS generation, package-aware simulation, crosstalk, and reflection analysis.
- Support layout reviews, silicon bring-up, characterization, debugging, and production ramp activities.
- Collaborate with system, package, reliability, product engineering, and physical design teams.
What you'll need
- 2–4 years of experience in analog/mixed-signal or IO circuit design.
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or a related field.
- Hands-on experience with custom circuit design using Cadence Virtuoso.
- Expertise with SPICE-based simulators such as Spectre, HSPICE, or FineSim.
- Understanding of CMOS device physics, analog circuit fundamentals, IO architectures, and ESD methodologies.
- Knowledge of LVS, DRC, EMIR, reliability checks, process corners, and Monte Carlo analysis.
- Strong analytical, debugging, communication, and cross-functional collaboration skills.
Nice to have
- Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.
- Knowledge of package modeling and SI/PI analysis tools.
- Experience with silicon validation, lab characterization, and IBIS/IBIS-AMI model generation.
- Scripting skills in Python, Perl, Tcl, or SKILL.
- Experience in automotive, AI/ML, networking, mobile, or data center SoCs.
Details
Read the full description and apply on the company’s own careers page.
