Senior DFT Designer

Overview

Senior DFT Designer role contributing to the development of mixed-signal and digital integrated circuits, designing, implementing and verifying DFT architectures for complex SoCs.

What you'll do

• Lead and execute the full DFT design flow, including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA) and verification.
• Develop and integrate scan insertion, test compression, and ATPG patterns.
• Implement memory BIST strategies.
• Collaborate closely with digital, analog, mixed-signal, product, test and software teams.
• Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• Develop and implement innovative DFT architectures and design methodologies to meet challenging performance, power, area and quality targets.
• Optimize test coverage, pattern count and test time.
• Perform comprehensive DFT verification at RTL and gate level.
• Work with ATE teams for test program development and silicon bring-up.
• Participate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality.
• Mentor junior engineers, provide technical guidance, and contribute to continuous improvement of DFT design processes and methodologies.
• Generate detailed design documentation, including specifications, test plans, and design reviews.
• Stay abreast of industry trends, emerging technologies, and best practices in digital IC design.

What you'll need

• Bachelor or master degree in microelectronics, ECE or related field.
• Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.
• Hands-on experience with industry standard ATPG tools.
• Proficiency in UPF/CPF-based low-power DFT.
• Knowledge of fault models (stuck-at, transition, path delay).
• Familiarity with physical design constraints for DFT.
• Experience in silicon debug and ATE bring-up.
• Knowledge of Verilog, SystemVerilog, VHDL.
• Strong commitment to schedule and quality, a good team player.