Senior Design Engineer

Overview

Senior Design Engineer responsible for designing, implementing, and verifying DFT architectures for complex SoCs, supporting testability and silicon quality.

What you'll do

• Define and implement SoC DFT architectures.
• Develop and integrate scan insertion, test compression, and ATPG patterns.
• Implement memory BIST and logic BIST strategies.
• Collaborate with RTL and physical design teams on DFT insertion and timing closure.
• Perform DFT verification at RTL and gate level.
• Support ATE test program development and silicon bring-up.
• Optimize test coverage, pattern count, and test time.

What you'll need

• Expertise in scan, MBIST, LBIST, and JTAG DFT methodologies.
• Hands-on experience with industry-standard ATPG tools.
• Proficiency in UPF/CPF-based low-power DFT.
• Knowledge of stuck-at, transition, and path-delay fault models.
• Familiarity with physical-design constraints for DFT.
• Experience in silicon debug and ATE bring-up.
• Bachelor’s or Master’s degree in Electrical or Electronics Engineering.

Nice to have

• Experience with SoC-level DFT.
• Exposure to high-speed interfaces and DFT for mixed-signal blocks.
• Strong problem-solving and communication skills.

Details

• Location: Noida