Senior Staff Engineer Design

Overview

Senior Staff Engineer responsible for designing and realizing complex digital signal processing hardware from RTL through silicon, including programmable filters and high-throughput data paths.

What you'll do

• Design Verilog RTL for arithmetic data paths, including multipliers, accumulators, pipelining, resource sharing and time-multiplexing.
• Design programmable filter hardware with coefficient tables and runtime bandwidth reconfiguration.
• Define numerical acceptance criteria and support UVM-based verification.
• Handle clock-domain crossing, reset architecture and timing closure for high-throughput data paths.
• Integrate register interfaces and AMBA AHB/APB on-chip buses.
• Take digital signal-processing solutions from RTL development through silicon.

What you'll need

• 7+ years designing digital signal-processing hardware in RTL.
• At least one product taken through to silicon.
• Expertise in Verilog RTL, fixed-point arithmetic and Q-format design.
• Experience implementing and verifying digital filters in fixed-point hardware.
• Understanding of filter behavior in closed-loop control systems, including bandwidth, group delay, phase and stability.
• Master’s degree in a relevant engineering field, or a bachelor’s degree with equivalent demonstrated DSP implementation experience.
• Experience with mixed-signal SoCs, UVM, AMBA integration, timing closure and CDC.

Nice to have

• Automotive or other safety-critical development experience to ISO 26262.
• Familiarity with requirements-driven development and Jama traceability tooling.

Details

• Location: Bangalore, India.