Senior/Staff NAND Design Rule Engineer

Overview

Drive and contribute to next-generation 3D NAND development within Process Integration, coordinating with peer groups and multidisciplinary teams to meet project milestones.

What you'll do

• Define physical design rules for current and future non-volatile memory technologies.
• Coordinate with process integration teams to keep design rules accurate and current.
• Evaluate layout and architecture options against design-rule and process limitations.
• Develop automated solutions and agentic capabilities for design-rule coverage and consistency.
• Investigate product and test-structure failures involving layout and mask data.
• Support design-rule checking for base and mask layers.
• Define algorithms for generating mask data from drawn base-layer data.

What you'll need

• At least 3 years of semiconductor-industry experience.
• Master’s or PhD degree.
• Experience in process integration, yield enhancement, product engineering, test-structure development, or unit-process development.
• Strong semiconductor device physics and VLSI silicon-processing knowledge.
• Ability to develop Python or other industry-standard programming solutions.
• Experience with layout and CAD tools including Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE.
• Strong knowledge of advanced semiconductor process flow and memory scaling.

Details

• Location: Hyderabad, India.