Senior Engineer, CAD Layout Automation

Overview

CAD Engineer role in a collaborative production support capacity, evaluating, improving and debugging in-house and commercial EDA tools and flows for physical layout, verification and design of CMOS integrated circuits, working with the Layout design teams to increase their productivity.

What you'll do

• Work closely with memory layout teams to solve their daily challenges and provide complete solutions for the future.
• Proactively identify problem areas for improvement, propose, and develop innovative solutions.
• Develop methodologies for highly reliable layout with a faster Time to Market approach.
• Lead layout flows implementation using AI-assisted and automated workflows, applying copilot-based assistants, agentic AI flows, and rule-aware automation to accelerate placement, routing and optimization.
• Continuously evaluate and implement new tools and technologies to improve the current layout development flows.
• Provide guidance and mentorship to junior members of the team.
• Develop and deploy AI-enabled methodologies for semi-automated floorplanning, parasitic estimation.

What you'll need

• 5+ years of experience in Layout automation, Physical Verification, or related domains.
• Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity.
• Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc.
• Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC-Extraction, ESD, and Latch-up.
• Good understanding of programming fundamentals, with exposure to various programming languages including Skill (Cadence), Perl, Python, Tcl.
• Working knowledge of Linux is a must.
• Excellent problem-solving skills with attention to detail.
• Ability to work in a dynamic environment.
• Proven expertise in defining, developing, and scaling AI-driven automation and AI-assisted methodologies for complex layout workflows.
• Proficiency in working effectively with global teams and stakeholders.
• A bachelor's or a master's degree in Electronics, Electrical or Computer Engineering.

Nice to have

• Working experience in PDN analysis tools like Totem/VoltusXFA/XA.
• Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues.
• Familiarity with machine learning frameworks such as PyTorch or scikit-learn.
• Experience integrating LLM APIs or related AI capabilities into engineering tools and workflows.