Senior Engineer – IC Verification

Overview

Design Verification Engineer on the IoT Digital team, verifying next-generation Wireless MCU SoCs alongside IC Design, System, and Architecture teams. Suited to an Engineer or Senior Engineer at IC3.

What you'll do

• Perform block- and IP-level verification to validate functionality, performance, and compliance with design requirements.
• Develop and execute verification plans based on architecture and design specifications, defining appropriate scenarios and closure criteria.
• Architect, implement, and maintain testbenches using SystemVerilog and UVM, including constrained-random stimulus, checkers, and assertions.
• Define and analyze functional coverage, identify gaps, and drive verification closure through coverage and regression analysis.
• Apply formal verification techniques to mixed-signal IP integration, including verification using real-number models (RNM).
• Integrate and verify SoC benches; define, test, and debug system use cases in collaboration with IC Design, System, and Architecture teams.
• Verify and debug low-power design behavior, including relevant power-management scenarios and interactions.
• Investigate failures, perform root-cause analysis, and communicate issues and verification status clearly to cross-functional teams.
• Improve verification flows and methodologies to streamline IP development, reuse, and integration.
• Contribute to reviews of specifications, verification plans, testbenches, and results, incorporating feedback to improve quality.
• Share reusable practices and technical learnings with the verification team.

What you'll need

• B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics, Computer Engineering, VLSI, or a related field.
• For Senior Engineer positions, typically 5 or more years of relevant IC design or Design Verification experience; Engineer-level candidates with a strong foundation will also be considered.
• Industry experience developing testbenches and verification components using SystemVerilog and UVM.
• Knowledge of verification planning, constrained-random testing, SystemVerilog Assertions (SVA), and functional coverage analysis.
• Experience with scripting or programming languages such as Python, Perl, Shell, or Tcl.
• Working knowledge of software or firmware coding in C and the ability to work with design specifications and debug simulation results.
• Understanding of low-power implementation and verification concepts, including UPF.
• Strong analytical, debugging, communication, and collaboration skills.

Nice to have

• Experience with wireless SoCs, low-power IoT silicon, or MCU subsystems.
• Experience with AMBA interconnect protocols, including AXI and APB, and embedded systems.
• Exposure to mixed-signal verification, real-number modeling (RNM), or SPICE-based simulation.
• Experience with formal verification, SoC bench integration, or low-power verification using UPF.
• Experience verifying security-related IP or features is an advantage.
• Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making.

Details

• Location: Hyderabad.
• Flexible work policy.