Senior Engineer, CAD Layout

Overview

Senior CAD Engineer responsible for improving EDA tools and automation flows supporting physical layout, verification, and CMOS integrated-circuit design. The role partners with memory layout teams to improve productivity through automated and AI-assisted methodologies.

What you'll do

• Support memory layout teams by solving daily challenges and developing lasting solutions.
• Identify layout-flow problems and develop improvements.
• Lead implementation of AI-assisted and automated layout flows.
• Develop methodologies for reliable layout and faster time to market.
• Evaluate and implement tools and technologies for layout development.
• Mentor junior team members.
• Deploy AI-enabled methods for semi-automated floorplanning and parasitic estimation.

What you'll need

• 5+ years of experience in layout automation, physical verification, or related domains.
• Experience customizing design environments and automation utilities for memory-layout productivity.
• Experience with place-and-route flows for custom memory layouts.
• Experience with tools such as Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, or Itools.
• Working knowledge of Linux.
• Programming fundamentals with exposure to Skill, Perl, Python, or Tcl.
• Bachelor’s or master’s degree in Electronics, Electrical, or Computer Engineering.

Nice to have

• Experience with Totem, VoltusXFA, or XA PDN analysis tools.
• Experience debugging DRC, ERC, LVS, DFM, antenna, Calibre, or ICV rule-deck issues.

Details

• Location: Hyderabad, Telangana, India.