Sr Layout Engineer-DPG-LPDDR

Overview

Senior Memory Layout Engineer-DPG-LPDDR role at Micron Technology, working on innovative memory and storage solutions in a dedicated team developing world-class products.

What you'll do

• Create bit cell layouts and perform pitch matching.
• Develop row decoder (XDEC) and column decoder (YDEC) layouts.
• Understand memory array hierarchy and decode paths.
• Implement custom layouts using Cadence Virtuoso.
• Run Calibre DRC/LVS checks, including debug and closure.
• Apply device physics expertise to drive layout implementation, including transistor matching strategies, well and substrate engineering, parasitic optimization, and EM/ESD reliability considerations.
• Independently plan, execute and deliver layout blocks with minimal supervision.
• Leverage AI/ML knowledge to support data-driven optimization, layout automation initiatives, and improved debug and correlation workflows.

What you'll need

• Hands-on experience on bit cell layout creation and pitch matching.
• Strong exposure to row decoder (XDEC) and column decoder (YDEC) layout development.
• 2+ years of proven experience in memory and full-custom layout development.
• Memory array hierarchy and decode path understanding.
• Proficient with Cadence Virtuoso for custom layout implementation.
• Solid experience with Calibre DRC/LVS, including debug and closure.
• Strong understanding of DRAM/LPDDR memory architecture, array organization, and peripheral integration.
• Strong device physics expertise.
• Strong ownership mindset with focus on quality, power and schedule.
• Education: B.Tech/B.E in Electronics, Electronics & Communications, or VLSI Engineering; or M.Tech in Electronics engineering, Microelectronics or VLSI Engineering.

Details

• Location: Hyderabad, Telangana, India.